1. Field of the Invention
The present invention relates to an interconnect structure, printed circuit board, a semiconductor device, and a manufacturing method for the interconnect structure.
2. Description of the Related Art
An interconnect pattern formed on a semiconductor device or a printed circuit board needs to have a sectional area corresponding to the amount of current flowing through interconnects in order to prevent excessive heating of the interconnects during current conduction.
For example, in a power device or a control device, an interconnect pattern for a power supply system involving a large amount of current needs to have a large sectional area. However, an increase in interconnect width is limited.
A method for further increasing current capacity without increasing the interconnect width is to increase the thickness of the interconnects or to form a pattern by using a plurality of conductive layers in a multilayer board in parallel.
However, the method of increasing the thickness of the interconnects has the disadvantages of needing more time to plate the interconnects and precluding miniaturization based on a reduction in interconnect intervals between signal lines through which a large current need not flow.
The method of using a plurality of conductive layers in a multilayer circuit board in parallel is limited in the increase in the number of conductive layers.
Japanese Patent Publication No. H10-32201 describes photolithography masks used to form interconnect patterns and including a mask in which all interconnect patterns are drawn as mask patterns and a mask in which only interconnect patterns for large currents are drawn as mask patterns. These masks are used to form a thick interconnect pattern for a large amount of current, while forming a thin interconnect pattern for a small amount of current, thus allowing miniaturization.
In Japanese Patent Publication No. 2007-165642, a groove is formed in an insulating resin on an interconnect layer and filled with a conductive paste, and surfaces that are not in contact with the conductive paste are plated with copper. This increases the current capacity per unit width of pattern in one layer.